As a control circuit for retaining the content stored in a CMOS memory or the like with the use of an auxiliary power supply, there is known a memory control circuit utilizing an output signal of a power supply monitor to protect the memory by means of a circuit causing the chip select signal of an SRAM to go high to thereby disable the memory when the power supply is cut off. As a known example of the described type, there is for example one disclosed in the gazette of Japanese Utility Model Laid-open No. Sho 62-23349.